Enable tailrec lower
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@@ -20,6 +20,7 @@ import org.jetbrains.kotlin.backend.common.lower.KCallableNamePropertyLowering
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import org.jetbrains.kotlin.backend.common.lower.LateinitLowering
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import org.jetbrains.kotlin.backend.common.lower.LocalFunctionsLowering
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import org.jetbrains.kotlin.backend.common.lower.SharedVariablesLowering
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import org.jetbrains.kotlin.backend.common.lower.TailrecLowering
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import org.jetbrains.kotlin.backend.common.runOnFilePostfix
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import org.jetbrains.kotlin.backend.jvm.lower.*
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import org.jetbrains.kotlin.ir.declarations.IrFile
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@@ -44,5 +45,7 @@ class JvmLower(val context: JvmBackendContext) {
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SingletonReferencesLowering(context).runOnFilePostfix(irFile)
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SyntheticAccessorLowering(context.state).lower(irFile)
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BridgeLowering(context.state).runOnFilePostfix(irFile)
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TailrecLowering(context).runOnFilePostfix(irFile)
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}
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}
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+15
-2
@@ -605,8 +605,21 @@ class ExpressionCodegen(
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val continueLabel = markNewLabel()
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val endLabel = Label()
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val condition = loop.condition
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gen(condition, data)
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BranchedValue.condJump(StackValue.onStack(condition.asmType), endLabel, true, mv)
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// Avoid true condition generation for tailrec
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// ASM and Java verifier assumes that L1 is reachable that cause several verification to fail,
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// to avoid them trivial jump elumination is required
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// L0
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// ICONST_1 //could be eliminated
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// IFEQ L1 //could be eliminated
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// .... // no jumps
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// GOTO L0
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// L1
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//TODO: write elimination lower
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if (!(condition is IrConst<*> && condition.value == true)) {
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gen(condition, data)
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BranchedValue.condJump(StackValue.onStack(condition.asmType), endLabel, true, mv)
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}
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with(LoopInfo(loop, continueLabel, endLabel)) {
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data.addInfo(this)
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