Order fixed in assignment instructions with qualified expression on a lhs

This commit is contained in:
Andrey Breslav
2013-12-03 18:12:03 +04:00
parent 28acbcb219
commit ef194ffe23
2 changed files with 11 additions and 17 deletions
@@ -358,21 +358,17 @@ public class JetControlFlowProcessor {
return;
}
if (left instanceof JetSimpleNameExpression) {
// Do nothing, only record write below
if (left instanceof JetSimpleNameExpression || left instanceof JetProperty) {
generateInstructions(rhs, false);
}
else if (left instanceof JetQualifiedExpression) {
// read the receiver
generateInstructions(rhs, false);
generateInstructions(((JetQualifiedExpression) left).getReceiverExpression(), false);
}
else if (left instanceof JetProperty) {
// do nothing, just write below
}
else {
builder.unsupported(parentExpression); // TODO
}
generateInstructions(rhs, false);
recordWrite(left, parentExpression);
}
+8 -10
View File
@@ -36,9 +36,9 @@ L0:
r(2) NEXT:[w(x)] PREV:[w(x)]
w(x) NEXT:[r(x)] PREV:[r(2)]
r(x) NEXT:[r(2)] PREV:[w(x)]
r(2) NEXT:[r(+=)] PREV:[r(x)]
r(+=) NEXT:[w(x)] PREV:[r(2)]
w(x) NEXT:[r(true)] PREV:[r(+=)]
r(2) NEXT:[call(+=, plus)] PREV:[r(x)]
call(+=, plus) NEXT:[w(x)] PREV:[r(2)]
w(x) NEXT:[r(true)] PREV:[call(+=, plus)]
r(true) NEXT:[jf(L2)] PREV:[w(x)]
jf(L2) NEXT:[r(2), r(1)] PREV:[r(true)]
r(1) NEXT:[jmp(L3)] PREV:[jf(L2)]
@@ -61,14 +61,12 @@ L4:
L5:
r(false && true) NEXT:[w(z)] PREV:[jf(L5), r(true)]
w(z) NEXT:[v(val t = Test())] PREV:[r(false && true)]
v(val t = Test()) NEXT:[r(Test)] PREV:[w(z)]
r(Test) NEXT:[r(Test())] PREV:[v(val t = Test())]
r(Test()) NEXT:[w(t)] PREV:[r(Test)]
w(t) NEXT:[r(1)] PREV:[r(Test())]
v(val t = Test()) NEXT:[call(Test, <init>)] PREV:[w(z)]
call(Test, <init>) NEXT:[w(t)] PREV:[v(val t = Test())]
w(t) NEXT:[r(1)] PREV:[call(Test, <init>)]
r(1) NEXT:[r(t)] PREV:[w(t)]
r(t) NEXT:[r(=)] PREV:[r(1)]
r(=) NEXT:[w(t.x)] PREV:[r(t)]
w(t.x) NEXT:[<END>] PREV:[r(=)]
r(t) NEXT:[w(t.x)] PREV:[r(1)]
w(t.x) NEXT:[<END>] PREV:[r(t)]
L1:
<END> NEXT:[<SINK>] PREV:[w(t.x)]
error: