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car_fmw: update cmsis lib system_stm32f4xx.c

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Without this USB VCP doesn't work
This commit is contained in:
Eugene Batalov
2016-07-14 13:39:57 +03:00
parent 8edad7335a
commit 91834ab403
1 changed files with 420 additions and 389 deletions
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car_fmw/src/lib/cmsis/system_stm32f4xx.c
+407 -376
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@@ -1,136 +1,143 @@
/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.c * @file system_stm32f4xx.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.0.1
* @date 30-September-2011 * @date 10-July-2012
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices, * This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool * and is generated by the clock configuration tool
* stm32f4xx_Clock_Configuration_V1.0.0.xls * stm32f4xx_Clock_Configuration_V1.0.1.xls
* *
* 1. This file provides two functions and one global variable to be called from * 1. This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings), * and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool. * depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and * This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file. * the "startup_stm32f4xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
* *
* 2. After each device reset the HSI (16 MHz) is used as system clock source. * 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program. * configure the system clock before to branch to main program.
* *
* 3. If the system clock source selected by user fails to startup, the SystemInit() * 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can * function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function. * add some code to deal with this issue inside the SetSysClock() function.
* *
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE * through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration. * value to your own configuration.
* *
* 5. This file configures the system clock as follows: * 5. This file configures the system clock as follows:
*============================================================================= *=============================================================================
*============================================================================= *=============================================================================
* Supported STM32F4xx device revision | Rev A * Supported STM32F4xx device revision | Rev A
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* System Clock source | PLL (HSE) * System Clock source | PLL (HSE)
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000 * SYSCLK(Hz) | 168000000
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000 * HCLK(Hz) | 168000000
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* AHB Prescaler | 1 * AHB Prescaler | 1
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB1 Prescaler | 4 * APB1 Prescaler | 4
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB2 Prescaler | 2 * APB2 Prescaler | 2
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000 * HSE Frequency(Hz) | 8000000
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_M | 25 * PLL_M | 8
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_N | 336 * PLL_N | 336
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_P | 2 * PLL_P | 2
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_Q | 7 * PLL_Q | 7
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLI2S_N | NA * PLLI2S_N | 352
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLI2S_R | NA * PLLI2S_R | 2
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* I2S input clock | NA * I2S input clock(Hz) | 176000000
*----------------------------------------------------------------------------- * |
* VDD(V) | 3.3 * To achieve the following I2S config: |
*----------------------------------------------------------------------------- * - Master clock output (MCKO): OFF |
* Main regulator output voltage | Scale1 mode * - Frame wide : 16bit |
*----------------------------------------------------------------------------- * - Error % : 0,0000 |
* Flash Latency(WS) | 5 * - Prescaler Odd factor (ODD): 1 |
*----------------------------------------------------------------------------- * - Linear prescaler (DIV) : 14 |
* Prefetch Buffer | OFF *-----------------------------------------------------------------------------
*----------------------------------------------------------------------------- * VDD(V) | 3,3
* Instruction cache | ON *-----------------------------------------------------------------------------
*----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode
* Data cache | ON *-----------------------------------------------------------------------------
*----------------------------------------------------------------------------- * Flash Latency(WS) | 5
* Require 48MHz for USB OTG FS, | Enabled *-----------------------------------------------------------------------------
* SDIO and RNG clock | * Prefetch Buffer | OFF
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*============================================================================= * Instruction cache | ON
****************************************************************************** *-----------------------------------------------------------------------------
* @attention * Data cache | ON
* *-----------------------------------------------------------------------------
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * Require 48MHz for USB OTG FS, | Enabled
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * SDIO and RNG clock |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY *-----------------------------------------------------------------------------
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING *=============================================================================
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE ******************************************************************************
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * @attention
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
****************************************************************************** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
*/ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f4xx_system /** @addtogroup stm32f4xx_system
* @{ * @{
*/ */
/** @addtogroup STM32F4xx_System_Private_Includes /** @addtogroup STM32F4xx_System_Private_Includes
* @{ * @{
*/ */
#include "stm32f4xx.h" #include "stm32f4xx.h"
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_Defines /** @addtogroup STM32F4xx_System_Private_Defines
* @{ * @{
*/ */
/************************* Miscellaneous Configuration ************************/ /************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted /*!< Uncomment the following line if you need to use external SRAM mounted
@@ -146,7 +153,7 @@
/************************* PLL Parameters *************************************/ /************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25 #define PLL_M 8
#define PLL_N 336 #define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */ /* SYSCLK = PLL_VCO / PLL_P */
@@ -155,281 +162,306 @@
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7 #define PLL_Q 7
/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
I2SCLK = PLLI2S_VCO / PLLI2S_R */
#define START_I2SCLOCK 0
#define PLLI2S_N 352
#define PLLI2S_R 2
/******************************************************************************/ /******************************************************************************/
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_Macros /** @addtogroup STM32F4xx_System_Private_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_Variables /** @addtogroup STM32F4xx_System_Private_Variables
* @{ * @{
*/ */
uint32_t SystemCoreClock = 168000000; uint32_t SystemCoreClock = 168000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{ * @{
*/ */
static void SetSysClock(void); static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F4xx_System_Private_Functions /** @addtogroup STM32F4xx_System_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the * Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable. * SystemFrequency variable.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit(void) void SystemInit(void)
{ {
/* FPU settings ------------------------------------------------------------*/ /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset CFGR register */
/* Set HSION bit */ RCC->CFGR = 0x00000000;
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CFGR = 0x00000000; RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEON, CSSON and PLLON bits */ /* Reset PLLCFGR register */
RCC->CR &= (uint32_t)0xFEF6FFFF; RCC->PLLCFGR = 0x24003010;
/* Reset PLLCFGR register */ /* Reset HSEBYP bit */
RCC->PLLCFGR = 0x24003010; RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset HSEBYP bit */ /* Disable all interrupts */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CIR = 0x00000000;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors, /* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/ AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock(); SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif #endif
} }
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real * 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may * frequency of the crystal used. Otherwise, this function may
* have wrong result. * have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* *
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp)
{ {
case 0x00: /* HSI used as system clock source */ case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04: /* HSE used as system clock source */ case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08: /* PLL used as system clock source */ case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P SYSCLK = PLL_VCO / PLL_P
*/ */
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0) if (pllsource != 0)
{ {
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
else else
{ {
/* HSI used as PLL clock source */ /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp; SystemCoreClock = pllvco/pllp;
break; break;
default: default:
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
} }
/* Compute HCLK frequency --------------------------------------------------*/ /* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */ /* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */ /* HCLK frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
/** /**
* @brief Configures the System clock source, PLL Multiplier and Divider factors, * @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings * AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration * @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function). * is reset to the default reset state (done in SystemInit() function).
* @param None * @param None
* @retval None * @retval None
*/ */
static void SetSysClock(void) static void SetSysClock(void)
{ {
/******************************************************************************/ /******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */ /* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/ /******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */ /* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON); RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */ /* Wait till HSE is ready and if Time out is reached exit */
do do
{ {
HSEStatus = RCC->CR & RCC_CR_HSERDY; HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++; StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET) if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{ {
HSEStatus = (uint32_t)0x01; HSEStatus = (uint32_t)0x01;
} }
else else
{ {
HSEStatus = (uint32_t)0x00; HSEStatus = (uint32_t)0x00;
} }
if (HSEStatus == (uint32_t)0x01) if (HSEStatus == (uint32_t)0x01)
{ {
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS; PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/ /* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/ /* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/ /* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */ /* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */ /* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */ /* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0) while((RCC->CR & RCC_CR_PLLRDY) == 0)
{ {
} }
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */ /* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL; RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */ /* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{ {
} }
} }
else else
{ /* If HSE fails to start-up, the application will have wrong clock { /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */ configuration. User can add here some code to deal with this error */
} }
/******************************************************************************/
/* I2S clock configuration */
/******************************************************************************/
#if START_I2SCLOCK
/* PLLI2S clock used as I2S clock source */
RCC->CFGR &= ~RCC_CFGR_I2SSRC;
/* Configure PLLI2S */
RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
/* Enable PLLI2S */
RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
/* Wait till PLLI2S is ready */
while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
} }
/** /**
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
* before jump to __main * before jump to __main
* @param None * @param None
* @retval None * @retval None
*/ */
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
/** /**
* @brief Setup the external memory controller. * @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main. * Called in startup_stm32f4xx.s before jump to main.
* This function configures the external SRAM mounted on STM324xG_EVAL board * This function configures the external SRAM mounted on STM324xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack). * This SRAM will be used as program data memory (including heap and stack).
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
/*-- GPIOs Configuration -----------------------------------------------------*/ /*-- GPIOs Configuration -----------------------------------------------------*/
/* /*
+-------------------+--------------------+------------------+------------------+ +-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment + + SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+ +-------------------+--------------------+------------------+------------------+
@@ -447,67 +479,67 @@ void SystemInit_ExtMemCtl(void)
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
| | PE15 <-> FSMC_D12 | | | PE15 <-> FSMC_D12 |
+-------------------+--------------------+ +-------------------+--------------------+
*/ */
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078; RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */ /* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc; GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xaaaa0a0a; GPIOD->MODER = 0xaaaa0a0a;
/* Configure PDx pins speed to 100 MHz */ /* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xffff0f0f; GPIOD->OSPEEDR = 0xffff0f0f;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */ /* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00cc0cc; GPIOE->AFR[0] = 0xc00cc0cc;
GPIOE->AFR[1] = 0xcccccccc; GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa828a; GPIOE->MODER = 0xaaaa828a;
/* Configure PEx pins speed to 100 MHz */ /* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc3cf; GPIOE->OSPEEDR = 0xffffc3cf;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */ /* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000; GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa; GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */ /* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff; GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */ /* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0; GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa; GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */ /* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff; GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/ /*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */ /* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001; RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */ /* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015; FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010603; FSMC_Bank1->BTCR[3] = 0x00010603;
FSMC_Bank1E->BWTR[2] = 0x0fffffff; FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/* /*
Bank1_SRAM2 is configured as follow: Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 3; p.FSMC_AddressSetupTime = 3;
@@ -533,21 +565,20 @@ void SystemInit_ExtMemCtl(void)
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/ */
} }
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/