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149 lines
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HTML
149 lines
6.0 KiB
HTML
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<title>Writing and Using MIPS exception handlers in MARS
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</title>
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<center>
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<h3>Writing and Using MIPS exception handlers in MARS</h3>
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</center>
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<h3>Introduction</h3>
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<i>Exception handlers</i>, also known as <i>trap handlers</i> or
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<i>interrupt handlers</i>, can easily be incorporated into a MIPS program.
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This guide is not intended to be comprehensive but provides the essential
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information for writing and using exception handlers.
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<p>Although the same mechanism services all three, <i>exceptions</i>, <i>traps</i>
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and <i>interrupts</i> are all distinct from each other.
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Exceptions are caused by exceptional conditions that occur at runtime
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such as invalid memory address references. Traps are caused by instructions
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constructed especially for this purpose, listed below. Interrupts are
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caused by external devices.
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<p>MARS partially but not completely implements the exception and interrupt
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mechanism of SPIM.
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<h3>Essential Facts</h3>
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Some essential facts about writing and using exception handlers include:
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<ul>
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<li>MARS simulates basic elements of the MIPS32 exception mechanism.</li>
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<li>The MIPS instruction set includes a number of instructions that
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conditionally trigger a trap exception based on the relative values of two
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registers or of a constant and a register:
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<tt>teq</tt>, <tt>teqi</tt> (trap if equal),
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<tt>tne</tt>, <tt>tnei</tt> (trap if not equal),
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<tt>tge</tt>, <tt>tgeu</tt>,
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<tt>tgei</tt>, <tt>tgeiu</tt> (trap if greater than or equal),
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<tt>tlt</tt>, <tt>tltu</tt>,
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<tt>tlti</tt>, <tt>tltiu</tt> (trap if less than)
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</li>
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<li>When an exception occurs,
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<ol>
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<li>Coprocessor 0 register $12 (status) bit 1 is set</li>
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<li>Coprocessor 0 register $13 (cause) bits 2-6 are set to the exception type (codes below)</li>
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<li>Coprocessor 0 register $14 (epc) is set to the
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address of the instruction that triggered the exception</li>
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<li>If the exception was caused by an invalid memory address,
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Coprocessor 0 register $8 (vaddr) is set to the invalid address.</li>
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<li>Execution flow jumps to the MIPS
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instruction at memory location <tt>0x800000180</tt>. This address
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in the kernel text segment (<tt>.ktext</tt> directive) is the
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standard MIPS32 exception handler location. The only way to change
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it in MARS is to change the MIPS memory configuration through
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the Settings menu item Memory Configuration.
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</li>
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</ol>
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</li>
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<li>There are three ways to include an exception handler in a MIPS program
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<ol>
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<li>Write the exception handler in the same file as the regular
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program. An example of this is presented below.
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</li>
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<li>Write the exception handler in a separate file, store that file
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in the same directory as the regular program, and select
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the Settings menu item "Assemble all files in directory"
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</li>
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<li>Write the exception handler in a separate file, store that file
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in any directory, then open the "Exception Handler..." dialog
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in the Settings menu, check the check box and browse to
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that file.
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</li>
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</ol>
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</li>
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<li>If there is no instruction at location <tt>0x800000180</tt>,
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MARS will terminate the MIPS program with an appropriate error message.
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</li>
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<li>The exception handler can return control to the program using
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the <tt>eret</tt> instruction. This will place the EPC register $14 value into the
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Program Counter, so be sure to increment $14 by 4 before returning
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to skip over the instruction that caused the exception. The <tt>mfc0</tt>
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and <tt>mtc0</tt> instructions are used to read from and write to Coprocessor 0
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registers.</li>
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<li>Bits 8-15 of the Cause register $13 can also be used to indicate
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pending interrupts. Currently this is used only by the Keyboard and
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Display Simulator Tool, where bit 8 represents a keyboard interrupt
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and bit 9 represents a display interrupt. For more details, see the
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Help panel for that Tool.
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</li>
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<li>Exception types declared in <tt>mars.simulator.Exceptions</tt>, but
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not necessarily implemented, are ADDRESS_EXCEPTION_LOAD (4), ADDRESS_EXCEPTION_STORE (5),
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SYSCALL_EXCEPTION (8),
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BREAKPOINT_EXCEPTION (9),
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RESERVED_INSTRUCTION_EXCEPTION (10),
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ARITHMETIC_OVERFLOW_EXCEPTION (12),
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TRAP_EXCEPTION(13),
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DIVIDE_BY_ZERO_EXCEPTION (15),
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FLOATING_POINT_OVERFLOW (16), and
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FLOATING_POINT_UNDERFLOW (17).
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</li>
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<li>When writing a non-trivial exception handler, your handler must first save
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general purpose register contents, then restore them before returning.</li>
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</ul>
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<h3>Example of Trap Handler</h3>
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The sample MIPS program below will immediately generate a trap exception because
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the trap condition evaluates true, control jumps to the exception handler,
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the exception handler returns control to the instruction following
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the one that triggered the exception, then the program terminates normally.
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<p>
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<pre>
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.text
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main:
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teqi $t0,0 # immediately trap because $t0 contains 0
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li $v0, 10 # After return from exception handler, specify exit service
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syscall # terminate normally
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# Trap handler in the standard MIPS32 kernel text segment
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.ktext 0x80000180
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move $k0,$v0 # Save $v0 value
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move $k1,$a0 # Save $a0 value
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la $a0, msg # address of string to print
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li $v0, 4 # Print String service
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syscall
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move $v0,$k0 # Restore $v0
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move $a0,$k1 # Restore $a0
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mfc0 $k0,$14 # Coprocessor 0 register $14 has address of trapping instruction
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addi $k0,$k0,4 # Add 4 to point to next instruction
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mtc0 $k0,$14 # Store new address back into $14
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eret # Error return; set PC to value in $14
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.kdata
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msg:
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.asciiz "Trap generated"
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</pre>
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<p></p>
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<h3>Widely Used Exception Handler</h3>
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The exception handler <tt>exceptions.s</tt> provided with
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the SPIM simulator will assemble and run under MARS. The MARS
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assembler will generate warnings because this program
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contains directives that it does not
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recognize, but as long as the setting "Assembler warnings are
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considered errors" is <i>not</i> set this will not cause any
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problems.
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</body>
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</html> |